A computer system, communication device, and other devices rely on memory to store instructions and data that are processed to perform various tasks. Substantial advances have been made over the years in both storage capacity and speed of memory devices for use in such applications. However, in some cases the speed of the memory has not kept pace with speed increases achieved with processors or other chips within the same system. Many applications require a memory device to be clocked at its maximum possible cycle time.
A memory array 105 contains an array of memory cells 110 connected to each other by row and column lines as shown in a self timed compiler memory device 100 illustrated in FIG. 1. Further as shown in FIG. 1, each row in the array of memory cells 110 is connected to a wordline (WL) 125 and each column in the array of memory cells 110 is connected to a bitline (BL) 130. Typically, before the wordlines (WLs) 125 in the array of memory cells 110 are activated, the bitlines (BLs) 130 are precharged. The memory device 100 has a timing circuit to determine when the BLs 130 have been completely precharged.
Also shown in FIG. 1, is a control block 115 including a design for test (DFT) 115A. Also, a row driver 120 drives a row of the memory cell 110 based on an internal clock generated by the control block 115. Further, a tracking circuit is used to set timing for a peripheral logic 150 turn on, based on a differential build up on the BLs 130 after the WLs 125 are turned on. For example, the peripheral logic 150 includes a sense amplifier, a write driver and/or a data latch. The tracking circuit includes a dummy WL (DWL) 135, an associated dummy BL (DBL) 140 and a DBL generation circuit 145. An internal clock at the tracking circuit triggers a signal, upon receiving the internal clock from the control block 115 that travels via the DWL 135, which in turn triggers the DBL 140 and travels back to the tracking circuit. This initiates a cycle reset process (e.g., the cycle path is shown by directional arrows 165 in FIG. 1), which turns on the BL 130 and a precharge circuit 160 precharges bitlines to prepare for a next read cycle.
It can be seen in the timing diagram 200 shown in FIG. 2 that during a read cycle, the BLs 130 are discharged only to a small extent (about 100 milli-volts) because of small size of transistors in memory cells. This small difference in BLs 130 is sensed through a sense amplifier. However, during the same read cycle, the logic low of the DBL 140 can go to zero much faster than the logic low of BLs 130, as discharge transistor sizes are multiple of transistor size of a single memory cell transistor. For example, the discharge driver transistor for the BL 130 is small (in order to keep area small) and hence the BL 130 discharges lower. However, as discharge transistors for the DBL 140 are in multiples of driver transistors size of memory cell 110, the DBL 140 discharges faster. It can be seen that precharging the DBL 140 back to logic high for the next read cycle can take a significantly longer time than time required to precharge the BL 130 back to the logic high. It can also be seen that this can significantly limit memory device cycle time as the BLs 130 would have precharged back to logic high at a significantly faster rate than the DBL 140 (as the BLs 130 do not discharge all the way to logic low of zero).